Various conventional techniques for circuit design have been disclosed. For example, according to a high-level synthesis method (first conventional example), a control data flow graph (CDFG) is generated based on an input file and a restriction file, and a finite state machine (FSM) is generated based on the CDFG and a constraint for a digital circuit. Then, according to the high-level synthesis method, nodes of the CDGF are allocated to states of the FSM to perform scheduling. Finally, according to the high-level synthesis method, resources are allocated to each node of the CDFG, based on resource level layout information indicative of the layout of resources for constructing the digital circuit, to generate circuit information (see, e.g., Japanese Laid-Open Patent Publication No. 2004-164627).
According to an automated circuit design method (second conventional example), a cell library for normal cells and specification information of a circuit to be designed are acquired, the upper limit potential of a virtual ground line in the circuit is set, and a cell library for low-threshold cells is generated using the upper limit potential. Then, according to the automated circuit design method, the specification information is logically synthesized to generate a net list, and a layout is generated based on the net list, the cell library for normal cells, and the cell library for low-threshold cells (see, e.g., Japanese Laid-Open Patent Publication No. 2005-135177).
A program converter (third conventional example) converts an operation description program describing a series of operation contents into a circuit description program describing the design contents of a circuit that implements the operation contents. The program converter then generates an index indicative of elements of a circuit that is obtained when the design contents described by the circuit description program is implemented using one or more hardware components (see, e.g., Japanese Laid-Open Patent Publication No. 2008-123103).
The above conventional techniques, however, provide no objective index on the scale of the circuit, which makes it difficult for a designer to understand the approximate circuit scale obtained as a result of high-level synthesis. Even if managing to understand the circuit scale, the designer still has difficulty in determining whether the circuit scale is too large or appropriate.